发明名称 |
NODE MEMORY SYSTEM FOR PARALLEL PROCESSING SYSTEM |
摘要 |
The interface of node memory and MBUS consists of a special controller chip and a multiple control module for data read/write operation in parallel processing system. The multiple control module comprises a type/size module for deciding the type/size of transaction, a 64 bit latch module for controlling the difference of data width at data input/output, a transmission module for controlling latch, a parity generation/check module for checking the effectiveness of input/output data a burst module for having 32 bit counter for burst transmission from 1byte to 128 byte, a module for generating self-address continuously without designating new address.
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申请公布号 |
KR950000495(B1) |
申请公布日期 |
1995.01.24 |
申请号 |
KR19910024777 |
申请日期 |
1991.12.28 |
申请人 |
KOREA ELECTRONICS & TELECOMMUNICAITONS RESEARCH INSTITUTE |
发明人 |
CHOE, JANG - SHIK;KIM, KI - HYON;LEE, HUN - BOK;PARK, CHI - HANG |
分类号 |
G11C7/00;(IPC1-7):G11C7/00 |
主分类号 |
G11C7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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