| 摘要 |
PURPOSE:To ensure the satisfactory noise reduction effect by sending the voltage of an intermediate level to an output terminal in an output preparing period. CONSTITUTION:In an output control circuit 6, the MOS transistors Q3 and Q4 are turned on and the NMOS TR Q9 and Q10 are turned off respectively when the output of an output preparing period detecting circuit 7 is kept at an L level. Then a buffer circuit 4 transmits a data signal. When the output of the circuit 7 is set at an H level, the TR Q3 and Q4 are turned off and the TR Q9 and Q10 are turned on respectively. Then an intermediate level of the voltage (1/2) VCC (power supply voltage) generated by an intermediate level generating circuit 8 is supplied to the circuit 4 as a power supply. Therefore the circuit 4 gives the intermediate level of the voltage (1/2) VCC to an output terminal 5 regardless of the output logical level of a latch circuit 3. |
