发明名称 PEAK DETECTION CIRCUIT
摘要 PURPOSE:To prevent an excess that output voltage rises more than input voltage and to perform a peak value detection exactly and at a high speed by reducing current charging a capacitor holding a peak value in accordance with the reduction of differential input voltage. CONSTITUTION:Current 11 and 12 is flown to each of first transistors Q2 and second Q3 according to the difference of output voltage Vo and input voltage Vin, when the voltage Vin and the output voltage Vo that a capacitor 17 holds matches, the matching is defined as I1-I2, and the drain current 15 of a transistor Q11 is defined as I2=I5 by the relation with a current mirror. Next, the current 15 flowing in the Q11 is made to be flown in the Q2 of a differential amplifier and the relation of I1=I5+I6 is formed in current. Because this expression is possible to be transformed like a I5=I1-I6, a voltage-current characteristic becomes the characteristic shown by the I5. Because a current source transistor Q12 charging the capacitor 17 and the Q4 flowing current 16 is in the relation of the current mirror, charging current becomes an analog to current 16 and becomes 0 by Vo=Vin if the Vo approaches Vin, and an overshoot charging will not be generated.
申请公布号 JPH0722924(A) 申请公布日期 1995.01.24
申请号 JP19930163690 申请日期 1993.07.02
申请人 FUJITSU LTD 发明人 MURAKAMI NORIO;MUKOUYAMA HIROYOSHI;UENO NORIO
分类号 H03K5/1532;G01R19/04 主分类号 H03K5/1532
代理机构 代理人
主权项
地址