| 摘要 |
PURPOSE: To make a speed higher at the time of the serial writing operation of a dual port memory, etc. CONSTITUTION: This serial data input device has latching means 32a to 32h for successively receiving and latching the serial data sequentially inputted to a data input buffer 28 and NMOS transmission gates 30a to 30h for switching data transmission routes to these latching means 32a to 32h. A master clock control signal SC is generated in synchronization with a signal clock SC. Shift register control signalsϕA toϕD are continuously generated at the quadruple period of the signalϕSC base on the signalϕSC. Latch control signalsϕ0 toϕ7 are continuously generated at the quadruple period of the signalϕA base on the signalϕA. The inputted serial data of 128 bits are once latched by the latching means 32a to 32h and are then once parallel outputted and are written into a data register when a data transmission control signalϕLOAD is impressed.
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