发明名称 CLOCK STABILIZING SYSTEM
摘要 PURPOSE:To stably generate a clock in a receiving station even when a power source of a transmitting station is disconnected, with regard to the clock stabilizing system for generating a stable clock in the other station in a digital radio transmission network. CONSTITUTION:When a primary power source of a transmitting station 1 is disconnected, a disconnection detecting circuit 7 detects it and sets a gate circuit to a gate 'closed' state. As a result, a clock from a clock converting part 4 is cut off by the gate circuit 10, and its input to a modulating part 3 is obstructed. When the clock comes not to be inputted, the modulating part 3 executes a non-modulating operation, and outputs a non-modulating signal. This non-modulating signal passes through a transmitting part 5, a transmitting antenna 6, a receiving antenna 12 and a receiving part 13 and is inputted to a clock extracting part 14. When this non-modulating signal is inputted, the clock extracting part 14 informs a clock synchronizing part 15 of disconnection of the clock, by which the clock synchronizing part 15 generates a clock by a free-running oscillating operation.
申请公布号 JPH0723036(A) 申请公布日期 1995.01.24
申请号 JP19930196658 申请日期 1993.06.30
申请人 NEC CORP 发明人 UENO TSUKASA
分类号 H04L7/00;H04B7/26;H04L27/00 主分类号 H04L7/00
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