| 摘要 |
PURPOSE:To provide the demodulator preventing the clock synchronizing stepout which is generated when a distortion occurs in the clock component in a demodulated baseband signal by fading. CONSTITUTION:Demodulated baseband signals outputted from nonlinear circuits 7 and 8 are divided into the input to a fixed delay circuit 14 and the input to a variable delay circuit 15. The signal with a constant delay given by the fixed delay circuit 15 and the signal with the proper amplitude and delay given by both the variable delay circuit 15 and an amplitude controller 16 are synthesized by a synthesizer 17 and then the clock is extracted. The variable delay circuit 14 and the amplitude controller 16 are controlled based on the tap coefficient of a judgement feedback type equalizer 13 and the distortion of the clock component by fading is equalized. Thus, the clock synchronization can be kept at the time of interference by fading. |
