发明名称 FRAME ALIGNER
摘要 <p>PURPOSE:To increase the margin to the jitter and the wander by providing plural delay amount and approach inhibition ranges, and selecting an optimal delay amount in accordance with a delay state and an approach state of a read-out timing of an elastic store. CONSTITUTION:Delay circuits 2-5 for delaying write data and a write frame pulse of an elastic store 1 by two kinds of delay amounts, respectively are provided, and selectors 6, 7 switch output signals of these delay circuits. Subsequently, the elastic store 1 sets an output signal of the selector 6 as write data, and sets an output signal of the selector 7 as a write timing. Also, approach inhibition range generating circuits 8, 9 generate an approach inhibition range before or after a read-out timing of the elastic store 1, a fact that the write timing of the elastic store 1 approaches these approach inhibition ranges is detected by phase comparators 10, 11, and by switching the selectors 6, 7 by its output information, an optimal signal is selected.</p>
申请公布号 JPH0723034(A) 申请公布日期 1995.01.24
申请号 JP19930164380 申请日期 1993.07.02
申请人 NEC CORP 发明人 IIZUKA EIJI
分类号 H04J3/06;H04L7/00;H04N5/073;(IPC1-7):H04L7/00 主分类号 H04J3/06
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