Semiconductor memory device having ECC circuit for decreasing the number of common bus lines to realize large scale integration and low power consumption

摘要

A semiconductor memory device has a cell and amplifier portion, a syndrome generation circuit, an error checking and correction circuit, and a plurality of memory control blocks. The cell and amplifier portion has a memory cell array, a sense amplifier array, and a column gate array, and each of the memory control blocks has a data bus amplifier, a write amplifier, and a syndrome decoder circuit which decodes syndrome output from the syndrome generation circuit. Consequently, an occupancy area can be reduced by decreasing the number of wiring lines, and a large scale integration and a low power consumption can be realized.