LAYOUT VERIFICATION SYSTEM,申请号JP19930164925-传众专利搜索

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发明名称	LAYOUT VERIFICATION SYSTEM
摘要
申请公布号	JPH0721247(A)	申请公布日期	1995.01.24
申请号	JP19930164925	申请日期	1993.07.05
申请人	NEC IC MICROCOMPUT SYST LTD	发明人	SUZUKI YASUSHI
分类号	G06F17/50;(IPC1-7):G06F17/50	主分类号	G06F17/50
代理机构		代理人
主权项
地址

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