发明名称 Packet assembler
摘要 Method and apparatus for reducing latency delay associated with converting asynchronous, serial digital data to packet data. The number of data characters received before a time-out occurs are counted; the last character received before a time-out occurs is recognized; or the number of data characters transmitted before a signal is received from the destination terminal are counted. The information thus gathered is used to predict the occurrence of future latency delay. Data packets are transmitted immediately upon the subsequent receipt of a number of data characters equal to the number of data characters received before the time-out occurred; receipt of a character identical to the last character received before a time-out; or receipt of a number of data characters equal to the number of data characters transmitted before another signal is received from the destination terminal, respectively. By transmitting immediately when a latency delay is expected, the latency delay is completely avoided.
申请公布号 US5384770(A) 申请公布日期 1995.01.24
申请号 US19920880218 申请日期 1992.05.08
申请人 HAYES MICROCOMPUTER PRODUCTS, INC. 发明人 MAYS, RICHARD C.;HAZZAH, KAREN G.;SAUSER, JR., MARTIN H.
分类号 H04L12/56;(IPC1-7):H04J3/24;H04L12/54 主分类号 H04L12/56
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