| 摘要 |
<p>The dual port video random access memory having the function of block write to reduce the layout area in integration is provided. The memory device comprises: cell array blocks, making each block out of multiple bitlines; column selective transistors, selecting each one among multiple bitlines, a 1st decoder, decoding the part of bits among column address signals and generating 1st selection signal for selecting cell array block; a 2nd decoder, decoding the rest of bits among column address signals and generating 2nd selection signal for selecting cell array block; a selective block, outputting block write signal accepted externally or 2nd selection signal selectively; transmission transistors, transferring the output signal of the selective block for controlling multiple column selective transistors.</p> |
