Pipelined memory having synchronous and asynchronous operating modes

摘要

A pipelined memory (20) has a synchronous operating mode and an asynchronous operating mode. The memory (20) includes output registers (34) and output enable registers (48) which are used to electrically switch between the asynchronous operating mode and the synchronous operating mode. In addition, in the synchronous operating mode, the depth of pipelining can be changed between a three stage pipeline and a two stage pipeline. By changing the depth of pipelining, the memory (20) can operate using a greater range of clock frequencies. In addition, the operating frequency can be changed to facilitate testing and debugging of the memory (20).