| 摘要 |
<p>PURPOSE:To transfer parallelly processed display data at a high speed by controlling a transfer operation based on control information on a mask memory. CONSTITUTION:Under the control of a memory controller 28, data on block transfer memories 30 are transferred through a bus interface 34 to a frame buffer 18. That is, corresponding to a start command from a CPU board 10 and in synchronism with clocks on an FB bus 16, transfer is started. At the time, the transmission of the data from the respective block transfer memories 30 to the FM bus 16 is controlled by the control information on the corresponding mask memories 32 and the collision of the data on the FM bus 16 is prevented. Also, since the transmission order of the data is the address order of the frame buffer 18, page mode access to the frame buffer 18, that is block transfer, can be executed. Thus, high speed transfer is realized without being accompanied by bus arbitration or the like and transfer time is not changed by the number of computing element substrates.</p> |
