METHOD OF SUPPORTING ARRANGEMENT OF SEMICONDUCTOR INTEGRATED CIRCUIT

摘要

A technique that allows a logic designer to perform in a short period of time an optimum arrangement, in terms of processing speed, of logic elements of a semiconductor integrated circuit. Logic blocks are arranged at desired locations on the display screen and the relation of connection among the logic blocks is displayed, using a logic block file which includes at least the names of logic blocks, the logic sizes and the connection relation among logic blocks. Referring to a logic block relation table, the logic designer can easily recognize the adequacy of the arrangement.