| 摘要 |
PURPOSE:To prevent the error in signal separation due to increase/decrease in a pointer value in mistake resulting from a bit error giving effect on judgement by majority decision for I or D bits. CONSTITUTION:A delay circuit 101 delays a signal 2 in modulation stage input signals 1-4 by one bit, the signal 3 is delayed by a delay circuit 102 by 2 bits, the signal 4 is delayed by the delay circuit 103 by 3 bits, the signal 1 through a differential coder 104, the signal 2 with one bit delay and passing through the differential coder 104, the signal 3 delayed by 2 bits, and the signal 4 delayed by 3 bits are inputted to a modulator 105, in which modulation is conducted. Then a modulation signal 7 is demodulated by a demodulator 106 and demodulated signals 8, 9 are decoded by a differential decoder 107, the signal 10 is delayed at the delay circuit 108 by 3 bits, the signal 11 is delayed by 2 bits at a delay circuit 109 and a signal 12 is delayed by one bit at a delay circuit 110 to disperse a bit error due to a signal point error of a modulation wave. |
