| 摘要 |
PCT No. PCT/DE92/00366 Sec. 371 Date Nov. 3, 1993 Sec. 102(e) Date Nov. 3, 1993 PCT Filed May 5, 1992 PCT Pub. No. WO92/20156 PCT Pub. Date Nov. 12, 1992.A logic circuit for asynchronous circuits, in which logic circuit signals which are present at the input (in) of the logic circuit can be linked both in a first logic block (NL) and also in a second logic block (PL) inverse thereto, and in which logic circuit, at a complete message output (cmpl), a signal can be formed to report valid data at an output (out) of the logic circuit, by a logic link (E), from signals from outputs of both logic blocks. In order to achieve a greater interference resistance and a lower power loss with the simultaneous use of conventional CMOS logic blocks, the first logic section is formed with n-channel transistors and the second logic section is formed with p-channel transistors and the outputs (A1 and A6) of the two logic sections are coupled to one another via transistors (8 and 10).
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