| 摘要 |
PURPOSE: To save an integrated circuit space by forming a circuit which generates a single pulse with time delay for detecting and exactly controlling input transition in plural input terminals of a few circuit elements. CONSTITUTION: Input signals I1 -In from plural input terminals are supplied to edge detecting blocks 10, and transition is detected, and plural pulses N1 -Nn are outputted from pulse generating blocks 11 connected with the blocks 10 in response to this detection. The pulses N1 -Nn are synthesized by an OR logical block 14, and set and reset signals are inputted to a latch block 15. A pulse delay element block 16 selects the exact amounts of reset signals for setting the width of the pulse issued from the block 15. Then, an output pulse is generated by transition in more than one input terminals according to the operation of the logical block 14. Thus, a circuit for detecting the input transition can be formed of a few circuit elements. |
