发明名称 ERROR CONTROL SYSTEM IN HOT STANDBY SYSTEM
摘要 PURPOSE:To perform the optimum control in the aspect of performance and reliability by using a processor relief function and an instruction retrial function in a hot standby system. CONSTITUTION:This system is an error control system in the hot standby system comprises in such a way that a system mode holding means 202, etc., which holds information to represent whether processors 10, 11, 20, and 21 comprising multiprocessors 1, 2 are current use systems or standby systems, and a means which transfers the content of the processor to another normal processor when an error with possible instruction retrial occurs and succeeds processing are included, and when the error with the possible instruction retrial occurs in one of the processors, the instruction retrial is performed in the processor in which the error occurs when the content of a system mode holding means are a 'standby mode', and the content of the processor in which the error occurs is transferred to another normal processor and the processing is continued when the contents are a 'current use system mode'.
申请公布号 JPH0713792(A) 申请公布日期 1995.01.17
申请号 JP19930158286 申请日期 1993.06.29
申请人 NEC CORP 发明人 YAMAMOTO YOSHINORI
分类号 G06F11/14;G06F11/20;G06F15/16;G06F15/177 主分类号 G06F11/14
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