| 摘要 |
<p>PURPOSE:To provide a bus transfer device which executes '0'-extending with a small hardware quantity. CONSTITUTION:When the output of a base register 3A is transmitted to a bus 1, at first, a precharge control circuit 2 is activated by a precharge control signal P/ and bus lines 11-18 are precharged to be '1' by the precharge control circuit 2. Then, tri-state buffers 51-54 are activated by an enable signal ENO. The output of the base register 3A is inverted in the tri-state buffers 51-54 and its inversion signal is transmitted to the bus lines 11-14 of a low-order 4 bits. At this time, bus transfer is executed by negative logic in this configuration so that the output of the base register 3A is '0'-extended so as to be transmitted to the bus lines 1<5>-1<8> of the high-order 4 bits. Therefore, the tri-state buffer for '0'-extending is unrequired and hardware quantity is reduced.</p> |
