Integrated logic circuit including impedance fault detection

摘要

An integrated logic circuit according to the present invention includes a plurality of logic circuit elements, such as field effect transistors, for performing a combinational logic function, and at least one test controlled-impedance element for loading the logic circuit and causing a first digital output signal to be produced when the impedance of a logic circuit element under test is within a predetermined range and produce another digital output signal when the impedance of the logic circuit element under test is outside the predetermined range. The test controlled-impedance elements typically comprise field effect transistors and are sized in accordance with a series of constraints. The constraints are obtained by considering the operation of the circuit under various impedance fault conditions (high, low and intermediate) and deriving a series of size relationships between the impedance values of the logic circuit and test elements. The impedance faults capable of being detected include the conventional stuck-on (LIF) arid stuck-off (HIF) impedance faults and also intermediate impedance faults (IHIF, ILIF) caused by a too high or too low an impedance in a transistor's on- and off-state modes of operation, respectively.