| 摘要 |
PURPOSE:To allow the circuit to automatically cope with the change in data speed by using a frequency detection means to detect coded data, inputting the data to a phase synchronization means and outputting a recovered clock. CONSTITUTION:A frequency detection section 1 consists of a counter 11, a maximum value circuit 12, a minimum value circuit 13 and an arithmetic operation circuit 14 and calculates frequency data from a maximum length and a minimum length of coded data in a logical H level. Then the coded data fin1 and a reference clock fc are inputted to the counter 11, which is operated by the clock fc and starts counting when the coded data fin1 is logical H and is reset in the logical L state. The output m1 of the counter 11 is inputted to the circuits 12, 13, which latch a maximum or a minimum decrement of the count m1 and provide an output of the result to the arithmetic operation circuit 14. The circuit 14 calculates the difference between the maximum decrement and the minimum decrement S1 to provide an output of frequency data (n). Even when a speed of the coded data is changed, the circuit corresponds therewith automatically without external change of the frequency and recovers the clock signal. |
