AUTOMATIC CLOCK LEVEL CONTROL CIRCUIT

摘要

PURPOSE:To surely compensate the level deviation of a received signal by monitoring the level of an output signal from a differential buffer concerning the circuit for automatically adjusting a voltage level at an end point at the time of transmitting a high-speed clock signal in an ECL level or the like by using a coaxial cable or the like and properly adjusting an input reference voltage to the differential buffer. CONSTITUTION:This circuit is provided with a differential buffer 1 for outputting a differential signal between the clock signal and an input reference voltage as a clock signal after level control, low-pass filter 6 for obtaining the average of output signals from the differential buffer 1, and operational amplifier 7 for feeding a differential signal between the average from the low- pass filter 6 and a set voltage corresponding to a prescribed level previously set concerning the clock signal back to the differential buffer 1 as the input reference voltage.