发明名称
摘要 The invention relates to an integrated circuit including one or more amorphous silicon layers for neutralizing charges which occur in various dielectric layers during fabrication. The amorphous silicon layers include dangling silicon bonds which neutralize charges which would otherwise cause isolation breakdown, impair integrated circuit performance and increase manufacturing costs.
申请公布号 JPH07500455(A) 申请公布日期 1995.01.12
申请号 JP19930507222 申请日期 1992.10.09
申请人 发明人
分类号 H01L21/76;H01L21/314;H01L21/316;H01L23/29;H01L23/532;H01L27/115;(IPC1-7):H01L21/76 主分类号 H01L21/76
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