发明名称 |
TECHNIQUES FOR IMPROVING MEMORY ACCESS IN A VIRTUAL MEMORY SYSTEM |
摘要 |
According to the present invention, methods and apparatus for reducing memory access latency are disclosed. When a new entry is made to translation look aside buffer (110), the new TLB entry points to a corresponding TLB page of memory (108). Concurrently with the updating of the TLB (110), the TLB page is moved temporally closer to a processor (102) by storing the TLB page in a TLB page cache (114). The TLB page cache (114) is temporally closer to the processor (102) than is a main memory (108).
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申请公布号 |
WO0045271(A1) |
申请公布日期 |
2000.08.03 |
申请号 |
WO2000US02403 |
申请日期 |
2000.01.27 |
申请人 |
INFINEON TECHNOLOGIES, AG;STRACOVSKY, HENRY |
发明人 |
STRACOVSKY, HENRY |
分类号 |
G06F12/08;G06F12/10;G06F13/16;(IPC1-7):G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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