ELIMINATION OF PARASITIC BJT CURRENT LEAKAGE PATH IN LOGIC CIRCUITS

摘要

The present invention is an apparatus and method to overcome the unwanted effects of parasitic bipolar discharge in silicon-on-insulator (SOI) field effect transistors (FET) (10) by eliminating the effects the sneak current discharging path by applying a contention free arrangement methodology to realize the dynamic logic circuit. The SOI MOS devices are arranged so as to eliminate the effects of electrical connections between certain intermediate nodes (88) of the dynamic logic circuit. Accordingly, eliminating any parasitic bipolar current leakage paths associated with such electrical connections between certain intermediate nodes of said stacked SOI MOS devices of said dynamic circuit (74).