Logic-circuit layout pattern inspection method and logical simulation

摘要

A circuit layout pattern inspection method and a logical simulator for implementing the same. Wiring is substituted by a pi or T equivalent circuit and is described by a nodal equation, and a gate is described by a simplified model, that is, a current source calculation formula. By the nodal equation and the current source calculation formula, a simulation is performed to obtain a delay time for every node. The obtained delay time is stored to make the inspection easy.