VIDEO SIGNAL PROCESSING SYSTEM

摘要

PURPOSE: To obtain a video signal processing system for converting a digital video sample locked to burst into a sample locked to a line. CONSTITUTION: A sample from an ADC 11 is supplied to a burst lock clock generator 12. This generator 12 generates a clock 4 Fsc with frequencies which are four times as high as those of a sub-carrier wave and the other clock signals Fsc and 2 Fsc. Those three kinds of clock signals generated by the clock generator 12 are impressed to a sample clock phase encoder 13. The phase encoder 13 generates a binary encoded word corresponding to the phase of a sampling clock cycle at that time. Also, a PCM sample outputted from the ADC 11 is supplied to a buffer memory 17 which converts a burst lock sample into a line lock sample rate.