| 摘要 |
PURPOSE:To suppress a transfer error to the minimum by providing a one input and many output selector at the input side of each sample-and-hold circuit. CONSTITUTION:This circuit is constituted of a one input and many output selector SEL, plural sample-and-hold circuits H1-H6 connected with the selector SEL, many input and many output multiplexer MUX connected with those sample-and-hold circuits H1-H6, plural multipliers M1-M6 connected with the multiplexer MUX, and adder ADD connected with those multipliers M1-M6. Therefore, the one input and many output selector SEL is provided at the input side of each sample-and-hold circuit H1-H6, so that it is not necessary to time- sequentially hold analog data, and transfer the data from one sample-and-hold circuit, for example, H1 through a transferring circuit to the other succeeding sample-and-hold circuits H2-H6. Thus, the data transfer error can be suppressed to the minimum. |
