| 摘要 |
PURPOSE:To apply asynchronous error characteristics to both of output voltage and counting time without requiring a steering circuit and a ternary input. CONSTITUTION:This counter generates the count output of a succeeding self- holding circuit under a condition of generating an output from a prestage self- holding circuit. These self-holding circuit respectively have logical operation oscillators OSC1 to OSC3, rectifier circuits RC1 to RC3 and delay circuits DE11, DE21. A count input pulse signal whose pulse width is not extended due to a failure is applied to the oscillators OSC1 to OSC3, and when a failure is generated in the circuit, no output is generated from the oscillators OSC1 to OSC3. Each of the delay circuits DE11, DE21 generates no failure on the shortened side of delay time. An output from each self-holding circuit has delay time longer than that of each delay circuit DE11 or DE21 and is inputted to the succeeding self-holding circuit under an AND condition with the count input pulse through a delay circuit DE12 or DE22 generating no failure on the shortened side of the delay time. |
