| 摘要 |
PURPOSE:To attain a serial-parallel conversion circuit of high speed and low power consumption. CONSTITUTION:High speed serial data are inputted and the retiming of the data is executed by the 1st high speed FF1 3 based upon high speed clock inputs. Differential two-frequency divided clocks prepared by dividing the frequency of the high speed clock inputs into too bands by the 2nd FF1 4 are applied to the 9th FF2 21 to 11th FF2 23 of medium speed to prepare eight frequency divided clocks and eight frequency divided shift clocks obtained by advancing the eight frequency divided clocks only by the half period of the two-frequency divided clock. The output of the 1st FF1 3 is inputted to a shift register constituted of the 1st FF2 13 to the 4th FF2 16 and the retiming of an output shifted by a positive phase two-frequency divided clock is executed by the 12th FF2 24 to the 15th FF2 27 based upon the eight-frequency divided shift clock. Similarly the retiming of an output from the 1st FF1 3 is executed by the 5th FF2 17 to the 8th FF2 20, the retiming of an output shifted by a reverse phase two- frequency divided clock is executed through the 16th FF2 28 to the 19th FF2 31 based upon the eight-frequency divided clock to obtain outputs from the 12th FF2 24 to the 19th FF2 31. |
