| 摘要 |
<p>PURPOSE: To simultaneously drive a plurality of cycles by using any processor pipeline to the utmost. CONSTITUTION: Each memory controller 156 utilizes each memory device having a different speed at the optimum speed of the memory device. A function is executed by a plurality of simple interdependent state machines bearing one small part and, when the function is completed, a related state machine is informed that it can execute and instructed to wait for or to proceed to the next start. The next state machine operates in a resemble fashion. A state machine which bears the first half part of a cycle starts its task before another state machine bearing the second half part of the cycle completes its task. Each memory controller 156 bears a certain interaction between its related bus and components and is logically organized as three main blocks, namely, a front end block, a memory block, and a host block interacting with each other together with other various blocks for handshaking.</p> |
