发明名称 CLOCK SIGNAL GENERATING DEVICE
摘要 <p>PURPOSE:To provide a normal result of majority decision even when the system of the voltage drop exists by inputting the clock signals of two other systems together with the output of a voltage monitoring circuit to monitor the output voltage into the majority decision circuit through the AND circuit to provide the logical product with the output. CONSTITUTION:When the voltage of the clock signal of the second system a2 among other systems becomes lower than the specified value, it is detected by a voltage monitoring circuit 4a of the first circuit part a1, and no signal is outputted to a clock synchronizing circuit 5a from that circuit, and the output to either of the input terminal of the AND circuit 10a is stopped. The AND circuit 10a stops the output of the clock signal from the second system a2 to a majority decision circuit 3 by this stop, and generates the specified clock signal and transmits it to a frequency multiplying circuit 8 and a frequency dividing circuit 2 based on the clock signals between the normal system a1 and the third system a3. Thus, the majority decision circuit 3 receives only the normal system to execute the majority decision to generate the clock signal, and the correction is correctly executed even when the system of the voltage drop appears.</p>
申请公布号 JPH072110(A) 申请公布日期 1995.01.06
申请号 JP19930167535 申请日期 1993.06.14
申请人 NIPPON SIGNAL CO LTD:THE 发明人 KAWAGUCHI TAKESHI
分类号 B61L19/06;G06F1/04;(IPC1-7):B61L19/06 主分类号 B61L19/06
代理机构 代理人
主权项
地址