| 摘要 |
<p>A bus circuit for implementing a high speed dominant logic bus for a differential signal. The bus circuit is useful in a communication network having a plurality of multi-port nodes that are coupled by point-to-point links that communicate differential signals. Each port (30) in the node includes a bus driver (150) that receives the differential signal received at the port. The bus driver supplies a differential current signal to a first bus (40). A terminator circuit (50) is coupled to the first differential bus, to receive the differential current signals supplied from the ports. The terminator circuit, responsive to the differential current signal, outputs a differential voltage signal indicative of either a dominant state or a non-dominant state to a second differential bus (42), which is coupled to the plurality of ports for transmission. A biasing circuit (80) for the bus drivers allows operation at low voltages, and furthermore insures that the zero crossing of the differential input signals is equivalent to the zero crossing of the differential voltage signal on the second differential bus.</p> |
