| 摘要 |
PCT No. PCT/EP92/01653 Sec. 371 Date Jan. 26, 1994 Sec. 102(e) Date Jan. 26, 1994 PCT Filed Jul. 20, 1992 PCT Pub. No. WO93/03501 PCT Pub. Date Feb. 18, 1993.The arrangement has storage cells consisting of MOS transistors and trench capacitors, the trench (7) being produced in a self-adjusted manner with respect to primary word lines (4) and insulation regions (2). Both capacitor electrodes are arranged within the trench, the first electrode being connected via a contact on the trench wall to the selection transistor. A bit line (20,21), which runs partially above and partially in the trench and is insulated from the second electrode (16) by a third and a fourth insulating layer (17,18) has a contact at this point to the conductive region of the adjacent selection transistor. The storage matrix is composed of rows of storage cells running in the direction of the bit line, the storage cells located in the same row having the selection transistor on a defined side of the capacitor, and on the opposite side in the adjacent row. A particularly high assessment reliability is achieved by two-layer metallization with a specific arrangement of primary, secondary and tertiary word lines (4', 40, 41).
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