发明名称 |
Write ordering for microprocessor depending on cache hit and write buffer content |
摘要 |
An improvement in a microprocessor having a cache memory providing strong and weak write ordering modes. The microprocessor includes a terminal for receiving a signal indicating whether an external write buffer is empty and an internal signal indicating whether an internal write buffer is empty. Operation of the microprocessor is halted in the strong ordering mode if the write buffers are not empty and a hit condition occurs during a write cycle until the buffers are empty.
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申请公布号 |
US5379396(A) |
申请公布日期 |
1995.01.03 |
申请号 |
US19910777765 |
申请日期 |
1991.10.11 |
申请人 |
INTEL CORPORATION |
发明人 |
GOCHMAN, SIMCHA;KAZACHINSKY, ITAMAR;KAGAN, MICHAEL |
分类号 |
G06F12/08;G06F12/10;(IPC1-7):G06F13/16 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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