| 摘要 |
A video motion compensation circuit comprising a Y phase variation compensation section for inputting a macro slice address signal and a motion vector Y signal and compensating for a variation in a phase of the motion vector Y signal and a X phase variation compensation section for inputting a macro block address signal and a motion vector X signal and compensating for a variation in a phase of the motion vector X signal. The X phase variation compensation section includes four logic circuits, each having a 2-bit shifter for inputting the macro block address signal of 7 bits and outputting a 9-bit signal, a logic adder for logically combining low order 2 bits of the motion vector X signal of 5 bits to previously add 1 to a LSB of the macro block address signal, and a complement operation unit/shifter for taking a 2's complement of the motion vector X signal of 5 bits and increasing a MSB of the 2's complement-operated signal to output a 9-bit signal. The Y phase variation compensation section includes a 4-bit shifter for inputting the macro slide address signal of 6 bits and outputting a 10-bit signal and a complement operation unit/shifter for taking a 2's complement of the motion vector Y signal of 5 bits and increasing a MSB of the 2's complement-operated signal to output a 10-bit signal.
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