发明名称 Semiconductor protecting apparatus and method for preventing destruction of internal circuit caused by latch-up
摘要 In a semiconductor integrated circuit device including a substrate bias voltage generating circuit supplying a substrate bias voltage to internal circuit performing original functions and a substrate where the internal circuit is formed, an N channel MOS transistor is provided between the internal circuit and power supply pad receiving an external voltage Vcc for driving the circuit. The transistor is controlled such that it is rendered conductive when substrate potential VSB is higher than the threshold voltage of MOS transistor and non-conductive when potential VSB is lower than the threshold voltage. Since supply of power supply voltage Vcc to the internal circuit is interrupted if latch-up is caused in the internal circuit and substrate potential VSB rises, internal circuit is immediately freed from the latch-up state even if latch-up is caused. Therefore, the internal circuit is protected from being heated or destructed by a current due to the latch-up.
申请公布号 US5379174(A) 申请公布日期 1995.01.03
申请号 US19920912368 申请日期 1992.07.13
申请人 MITSUBISHI DENKI KABUSHIKI KAISHA 发明人 KASAMOTO, MASAYUKI
分类号 H01L27/06;H01L27/02;(IPC1-7):H02H9/02 主分类号 H01L27/06
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