| 摘要 |
An apparatus and method are provided for simplifying a finite field division, including inputs for the initial condition signals a(x), b(x), and p(x), and providing at an output node the signal c(x), where c(x)=a(x)/b(x) without intermediate inverter circuitry for finding 1/b(x). A reference register initialized to b(x), and a divider register initialized to a(x). Both registers are manipulated in parallel by a logic circuit which responds to the contents of the reference register, converting its contents to 1.Claim By applying the same manipulations to the divider register, its contents are converted from a(x) to a(x)/b(x). One embodiment of a finite field divider according to the present invention is used to provide a single finite field division of a single set of values a(x), b(x) and p(x). Another embodiment processes continuous streams of a(x), b(x) and p(x) values, to provide a continuous stream of c(x) values delayed by a calculation time. In yet another embodiment, p(x) is not a stream of values, but a constant either applied to the p(x) input of the finite field divider circuit or a constant defined by fixed circuit elements within the divider circuit.
|
