发明名称 System using separate transfer circuits for performing different transfer operations respectively and scanning I/O devices status upon absence of both operations
摘要 An I/O controller for transferring data between a host processor and one or more I/O units. The controller interleaves processor command transfers (PIO) in the midst of direct memory access (DMA) transfers without repeated data moves. DMA transfers are suspended temporarily during the priority PIO transfer. An interrupt Scanner, for scanning the various I/O units, is also prioritized with respect to DMA and PIO transfers.
申请公布号 US5379381(A) 申请公布日期 1995.01.03
申请号 US19910743992 申请日期 1991.08.12
申请人 STRATUS COMPUTER, INC. 发明人 LAMB, JOSEPH M.
分类号 G06F13/12;G06F13/28;G06F13/32;(IPC1-7):G06F13/00 主分类号 G06F13/12
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