| 摘要 |
A delay compensating circuit for equalizing the propagation and processing delays from data sources which are read sequentially by a central data processing unit. Data from individual data sources is multiplexed into a real-time composite data stream which contains data from each data source and in which the final data bit from one source is followed, during the next clock cycle, by the first data bit from the next data source. To achieve this order, the total (propagation and processing) delay from each data source is controlled to a fixed amount by adding a compensating delay to each data source and adjusting delay automatically following each data transfer based on the occurrence of a known data transition in each data frame.
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