发明名称 Method of semiconductor via testing
摘要 A semiconductor wafer having a via test structure is provided which includes a semiconductor substrate having a plurality of semiconductor devices. A dielectric layer deposited over the semiconductor substrate has second and fourth channels unconnected to the plurality of semiconductor devices. A via dielectric layer deposited over the channel dielectric layer has first and second vias and third and fourth vias respectively open to opposite ends of the second channel and the fourth channel. A second dielectric layer over the via dielectric layer has first, third, and fifth channels respectively connected to the first via, the second and third vias, and the fourth via. The first channel, the first via, the second channel, the second via, the third channel, the third via, the fourth channel, the fourth via, and the fifth channel are connected in series and the first and fifth channel are probed to determine the presence or absence of voids in the vias.
申请公布号 US6858511(B1) 申请公布日期 2005.02.22
申请号 US20020256805 申请日期 2002.09.26
申请人 ADVANCED MICRO DEVICES, INC. 发明人 MARATHE AMIT P.
分类号 H01L21/66;(IPC1-7):H01L21/331;H01L21/76 主分类号 H01L21/66
代理机构 代理人
主权项
地址