A gate turn-off thyristor including: an n-type emitter semiconductor layer (13) divided into a plurality of n-type areas; a p-type base semiconductor layer (14) which cooperates with the n-type emitter semiconductor layer to form a first main circular surface (11); an n-type base semiconductor layer (15); and a p-type emitter semiconductor layer (16) cooperating with the n-type base semiconductor layer to form a second main circular surface (12). A first main electrode (2) put in low resistance contact with the n-type emitter semiconductor layer is formed on the first main surface. A second main electrode (3) put in low resistance contact with the p-type emitter layer and the n-type base semiconductor layer is formed on the second main surface. A control electrode (4) is formed in the p-type base semiconductor on the first main surface. An outer diameter of the p-type emitter semiconductor layer (rPE) is smaller than that of the n-type emitter semiconductor layer (rNE). This reduces the current in the peripheral region and ensures a higher switching speed as the peripheral thyristor region is not overheated. Other ways of reducing the current in the peripheral region include introduction of lifetime killers or lowering the doping of the p-type emitter layer (16) in the peripheral region. <IMAGE>
