| 摘要 |
A successive-approximation register (SAR) has a single shift register for processing, that is presetting and selectively resetting, a number of bits. The single shift register is arranged to provide bit selection for processing the bits and also to provide desired result accumulation in the processed bits. Further, the single shift register comprises an array of stages, the stages including a first stage, a last stage and a number of active stages equal to the number of bits of digital output. Conveniently, the SAR adopts a "One-bits to Right" test implemented by a Manchester Carry Chain in the opposite direction to the shift direction.
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