发明名称 Method for forming vertical transistor structures having bipolar and MOS devices
摘要 A transistor is formed as either a bipolar transistor (10) or an MOS transistor (11). Each transistor (10 or 11) has a substrate (12). Bipolar transistor (10) has a first current electrode (26) underlying a control electrode (28), and a second current electrode (32) overlying the control electrode (28). MOS transistor (11) has a first current electrode (54) underlying a channel region (56), and a source lightly doped region (58) and a source heavily doped region (60) overlying the channel region (56). A control electrode conductive layer (40) is laterally adjacent a sidewall dielectric layer (48), and sidewall dielectric layer (48) is laterally adjacent channel region (56). Conductive layer (40) functions as a gate electrode for transistor (11). Each of the transistors (10 and 11) is vertically integrated such as in a vertically integrated BiMOS circuit. Transistors (10 and 11) can be electrically isolated by isolation ( 64 and 66).
申请公布号 US5376562(A) 申请公布日期 1994.12.27
申请号 US19930065419 申请日期 1993.05.24
申请人 MOTOROLA, INC. 发明人 FITCH, JON T.;MAZURE, CARLOS A.;WITEK, KEITH E.;HAYDEN, JAMES D.
分类号 H01L21/8249;H01L21/331;H01L21/336;H01L21/822;H01L27/06;H01L29/73;H01L29/732;H01L29/78;(IPC1-7):H01L21/265 主分类号 H01L21/8249
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