| 摘要 |
An improved N-channel field-effect transistor is fabricated by performing a vertical N- implant, aligned to the vertical edges of the gate electrode, in both the source and drain regions of the device. In a first embodiment of the invention intended for use in dynamic random access memory access devices, a dielectric spacer is then formed on the sidewall of the gate electrode adjacent the drain (i.e., the regions which functions as the bitline contact in a DRAM memory cell). A vertical N+ implant, aligned to the exposed vertical edge of that spacer, is performed, in addition to an oblique implant of an N-type impurity. The oblique implant dosage is significantly greater than the N- implant dosage, but significantly less than the N+ implant dosage. In a second embodiment of the invention intended for use in applications where the transistor has no capacitive storage node, spacers are formed on both sidewalls of the gate electrode and the N+ implant, as well as the oblique N-type implant are performed in both the source and drain regions of the device. In preferred embodiments of the invention, phosphorus is utilized as the N- implant impurity, while arsenic is utilized for the other two N-type implants. The oblique implant provides not only reduced electric field strength in the channel region, but also reduced series resistance.
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