发明名称 Bidirectional wait control between host module and slave module
摘要 A bidirectional wait control system for controlling data movement between a slower-speed host module and a faster-speed slave module by means of a bus interface, comprises: a first wait control signal generating means in the host module, capable of generating a first wait control signal synchronizing with that of the bus interface; a second wait control signal generating means in the slave module, responsive to the first wait control signal, capable of generating a second wait control signal synchronizing with that of the bus interface; and means, upon each module having been presented with the wait control signal from the other module, for terminating data movement between the host module and the slave module.
申请公布号 US5377325(A) 申请公布日期 1994.12.27
申请号 US19920871409 申请日期 1992.04.21
申请人 ACER INCORPORATED 发明人 CHAN, WAN-KAN
分类号 G06F13/42;(IPC1-7):G06F13/00 主分类号 G06F13/42
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