The DRAM column address control circuit using the address transition detector has no delay in reading the input data since the data is read in differential type of data bus sense amplifier when the column address is changed. The control circuit comprises a column address buffer (1); a column address predecoder (8); an address transition detector (2); a transition pulse generator (3); a column redundancy circuit (4); an Y-decoder (9); a spare Y-decoder (7); and a data sense amplifier (11). The data bus sense amplifier is in the differential type and can read the output signal of Y-decoder or spare Y-decoder without an enable signal generator.
