发明名称 |
CONDUCTING WIRING MANUFACTURING METHOD USING PLANARIZATION OF POLYSILICON LAYER |
摘要 |
The method includes the steps of etching the insulating layer (21) and conductive layer (10) to form a contact hole (22), planarizing a polysilicon layer (23) for conductive wiring, etching the layer (23) at a predetermined thickness to flatten the layer (23) on the multilayered wiring structure, and etching the layer (23A) by mask patterning process to form a conductive wiring on the substrate. Pref. the layer (23) is formed to 6000 angstroms and etched back to 5000 angstroms in thickness.
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申请公布号 |
KR940011735(B1) |
申请公布日期 |
1994.12.23 |
申请号 |
KR19910022563 |
申请日期 |
1991.12.10 |
申请人 |
HYUNDAI ELECTRONICS CO., LTD. |
发明人 |
LEE, HYON - CHOL;YUN, SU - SHIK;SON, KON;KIM, MYONG - SON;KIM, IL - UK;PARK, HAE - SONG |
分类号 |
H01L21/28;(IPC1-7):H01L21/28 |
主分类号 |
H01L21/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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