| 摘要 |
PURPOSE:To read the contents of an arbitrary gate in a gate array from outside by a method wherein ECL gates are two dimensionally arranged, one test selection signal wire is connected to each test selection signal terminal in a direction, and the other test output signal wire is connected to each test output signal terminal in other direction. CONSTITUTION:For an ECL gate array 230, ECL logic gate arrays 200-203 are arranged on an array, each test selection signal terminal is connected to a test selection signal wire 210 from a test signal control circuits 204 and 211, and each test output signal terminal is connected to test output signal wires 212 and 213 to the test output control circuit 205. When testing a logic gate 200, the internal state of the logic gate 200 is fed to the test output signal wire 212 by selecting the test selection signal wire 210. Thus, by selecting a desired test selection signal wire, it is possible to read the internal state of the ECL logic gate in an arbitrary line. |
