| 摘要 |
PURPOSE:To accurately transfer a signal regardless of a high clock frequency. CONSTITUTION:A variable delay buffer 10 of a PLL circuit 1 delays the input clock signal inputted from a clock input terminal 14 and outputs the output clock signal to a clock output terminal 15. A frequency divider circuit 11 divides the frequency of the input clock signal to the variable delay buffer 10 by an integer and outputs the frequency divided clock signal to an output terminal 16 as an input clock phase comparison signal. A frequency divider circuit 12 divides the frequency of the output clock signal from the variable delay buffer 10 by an integer and outputs the frequency divided clock signal to an output terminal 17 as an output clock phase comparison signal. A phase comparator 13 compares the phase of the input clock phase comparison signal inputted from an input terminal 18 and that of the output clock phase comparison signal inputted from an input terminal 19 with each other and adjusts the extent of delay of the variable delay buffer 10 in accordance with the comparison result. |
